SH7280 Datasheet, PDF (1376/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.19 USB Endpoint Stall Register (USBEPSTL)
The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit
is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for
endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which
decoding is performed in this function module. When the SETUPTS flag in USBIFR0 is set,
writing 1 to the EP0STL bit is ignored. For details, see section 25.7, Stall Operations. When
ASCE = 1 is specified, the EPxSTL bit is automatically cleared.
USBEPSTL can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
-
- ASCE EP3STL EP2STL EP1STL EP0STL
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W
Bit
7 to 5
Bit Name

Initial
Value
All 0
4
ASCE
0
3
EP3STL
0
2
EP2STL
0
1
EP1STL
0
0
EP0STL
0
R/W Description
R Reserved
The write value should always be 0.
R/W Auto-Stall Clear Enable
When this bit is set to 1, the stall setting bit
(USBEPSTLR/ESxSTL) of the USB endpoint is
automatically cleared after a stall handshake is
returned to the host. This bit cannot be set for each
endpoint.
R/W EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
R/W EP2 Stall
When this bit is set to 1, endpoint 2 is placed in the
stall state.
R/W EP1 Stall
When this bit is set to 1, endpoint 1 is placed in the
stall state.
R/W EP0 Stall
When this bit is set to 1, endpoint 0 is placed in the
stall state.
Rev. 1.00 Jun. 26, 2008 Page 1346 of 1692
REJ09B0393-0100