SH7280 Datasheet, PDF (1366/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.10 USBEP1 Data Register (USBEPDR1)
USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When one packet of data is
received normally from the host, the EP1FULL bit in USB interrupt flag register 0 is set. The
number of receive bytes is indicated in the EP1 receive data size register. After the data has been
read, the buffer that was read is enabled to receive again by writing 1 to the EP1RDFN bit in the
USB trigger register. The receive data in this FIFO buffer can be transferred by DMA or DTC
(dual address transfer byte by byte).
USBEPDR1 can be initialized by means of the EP1CLR bit in USBFCLR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
31 to 0* D31 to D0 Undefined R
Data register for endpoint 1 transfer
Note: * 7 to 0 bits for DMA or DTC transfer.
Rev. 1.00 Jun. 26, 2008 Page 1336 of 1692
REJ09B0393-0100