SH7280 Datasheet, PDF (757/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 14 Compare Match Timer (CMT)
Initial
Bit
Bit Name Value R/W Description
5 to 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0
CKS[1:0] 00
R/W Clock Select
These bits select the clock to be input to CMCNT from
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS[1:0].
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 1.00 Jun. 26, 2008 Page 727 of 1692
REJ09B0393-0100