SH7280 Datasheet, PDF (1390/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.5.6 EP3 Interrupt-IN Transfer
USB function
Application
IN token reception
Valid data
in EP3 FIFO?
Yes
No
NACK
Data transmission to host
Is there data
No
for transmission
to host?
Yes
Write data to USBEP3 data
register (USBEPDR3)
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
ACK
Set EP3 transmission
complete flag
(USBIFR1/EP3 TS = 1)
Interrupt request
Clear EP3 transmission
complete flag
(USBIFR1/EP3 TS = 0)
Is there data
No
for transmission
to host?
Yes
Write data to USBEP3 data
register (USBEPDR3)
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register
is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 25.12 EP3 Interrupt-IN Transfer Operation
Rev. 1.00 Jun. 26, 2008 Page 1360 of 1692
REJ09B0393-0100