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SH7280 Datasheet, PDF (248/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
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Section 8 Data Transfer Controller (DTC)
Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included)
1st Transfer
2nd Transfer
Transfer
Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*1 CHNE CHNS RCHNE DISEL Counter*1 DTC Transfer
Normal 0


0
Not 0





Ends at 1st
transfer
0


0
0
0


1











Ends at 1st
transfer
Interrupt request
to CPU
1
0



0


0
Not 0
Ends at 2nd
transfer
0


0
0
0


1

Ends at 2nd
transfer
Interrupt request
to CPU
1
1

0
Not 0





Ends at 1st
transfer
1
1

1
Not 0





Ends at 1st
transfer
Interrupt request
to CPU
1
1


0
0


0
Not 0
Ends at 2nd
transfer
0


0
0
0


1

Ends at 2nd
transfer
Interrupt request
to CPU
Rev. 1.00 Jun. 26, 2008 Page 218 of 1692
REJ09B0393-0100
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