SH7280 Datasheet, PDF (18/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) ................................ 681
12.1 Input/Output Pins.............................................................................................................. 684
12.2 Register Descriptions........................................................................................................ 685
Section 13 Port Output Enable 2 (POE2) ............................................................ 689
13.1 Features............................................................................................................................. 689
13.2 Input/Output Pins.............................................................................................................. 691
13.3 Register Descriptions........................................................................................................ 693
13.3.1 Input Level Control/Status Register 1 (ICSR1) ................................................ 694
13.3.2 Output Level Control/Status Register 1 (OCSR1) ............................................ 698
13.3.3 Input Level Control/Status Register 2 (ICSR2) ................................................ 699
13.3.4 Output Level Control/Status Register 2 (OCSR2) ............................................ 703
13.3.5 Input Level Control/Status Register 3 (ICSR3) ................................................ 704
13.3.6 Software Port Output Enable Register (SPOER) .............................................. 706
13.3.7 Port Output Enable Control Register 1 (POECR1)........................................... 708
13.3.8 Port Output Enable Control Register 2 (POECR2)........................................... 709
13.4 Operation .......................................................................................................................... 715
13.4.1 Input Level Detection Operation ...................................................................... 717
13.4.2 Output-Level Compare Operation .................................................................... 718
13.4.3 Release from High-Impedance State ................................................................ 719
13.5 Interrupts........................................................................................................................... 720
13.6 Usage Notes ...................................................................................................................... 721
13.6.1 Pins States when the Watchdog Timer has Issued a Power-on Reset ............... 721
Section 14 Compare Match Timer (CMT) .......................................................... 723
14.1 Features............................................................................................................................. 723
14.2 Register Descriptions........................................................................................................ 724
14.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 725
14.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 726
14.2.3 Compare Match Counter (CMCNT) ................................................................. 728
14.2.4 Compare Match Constant Register (CMCOR) ................................................. 728
14.3 Operation .......................................................................................................................... 729
14.3.1 Interval Count Operation .................................................................................. 729
14.3.2 CMCNT Count Timing..................................................................................... 729
14.4 Interrupts........................................................................................................................... 730
14.4.1 Interrupt Sources and DTC/DMA Transfer Requests....................................... 730
14.4.2 Timing of Compare Match Flag Setting ........................................................... 730
14.4.3 Timing of Compare Match Flag Clearing......................................................... 731
Rev. 1.00 Jun. 26, 2008 Page xviii of xxx