SH7280 Datasheet, PDF (1671/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
31.3.11 Serial Communication Unit (SSU) Timing
Table 31.15 Serial Communication Unit (SSU) Timing
Conditions: V_CC = 3.0 to 5.5 V, AV_CC = AVREF = 4.5 to 5.5V,
V_SS = PLLV_SS = AVREFVSS = AV_SS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Clock cycle
Master
t_SUcyc
4
Slave
4
Clock high pulse width
Master t
40
HI
Slave
40
Clock low pulse width
Master t
40
LO
Slave
40
Clock rise time
Clock fall time
Data input setup time
t_RISE
—
t
—
FALL
Master
t_SU
25
Slave
30
Data input hold time
Master
t_H
10
Slave
10
SCS setup time
Master t
1.5
LEAD
Slave
1.5
SCS hold time
Master t
1.5
LAG
Slave
1.5
Data output delay time
Master t
—
OD
Slave
—
Continuous transmission
Master
t_TD
1.5
delay time
Slave
1.5
Slave access time
t
—
SA
Slave out release time
t
—
REL
Note: t_pcyc indicates peripheral clock (Pφ) cycle.
Max.
—
—
—
—
—
—
20
20
—
—
—
—
—
—
—
—
40
40
—
—
1
1
Unit
t_pcyc
ns
Figure
Figures
31.49, 31.50,
31.51, 31.52
ns
ns
ns
ns
ns
t
pcyc
t
pcyc
ns
t_pcyc
t
Figure 31.51
pcyc
t
Figure 31.52
pcyc
Rev. 1.00 Jun. 26, 2008 Page 1641 of 1692
REJ09B0393-0100