SH7280 Datasheet, PDF (331/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
9.4.8 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of DTC or DMAC bus release. It is used to
give priority to DTC or DMAC transfer or reduce the number of cycles in which the DTC is
active.
For the differences in DTC operation according to the combinations of the DTLOCK and DTBST
bit settings, refer to section 8.5.9, DTC Bus Release Timing.
Setting the DTSA bit enables DTC short address mode. For details of the short address mode, see
section 8.4, Location of Transfer Information and DTC Vector Table.
The DTPR bit selects the DTC activation priority used when multiple DTC activation requests are
generated before DTC activation.
Do not modify this register while the DMAC or DTC is active.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DT
LOCK
-
-
- DTBST DTSA - DTPR -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R/W R/W R R/W R R R R R R R R
Bit
Bit Name
15
DTLOCK
14 to 12 
Initial
Value
0
All 0
R/W Description
R/W DTC Lock Enable
Specifies the timing of DTC bus release.
0: The DTC releases the bus when the NOP instruction
is issued after vector read, or after write-back of
transfer information is completed.
1: The DTC releases the bus after vector read, when
the NOP instruction is issued after vector read, after
transfer information read, after a single data transfer,
or after write-back of transfer information.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 301 of 1692
REJ09B0393-0100