SH7280 Datasheet, PDF (1714/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Conflict between NMI Interrupt
and DTC Activation................................ 243
Conflict between word-write
and count-up processes of CMCNT ....... 733
Conflict between write
and compare-match processes
of CMCNT.............................................. 732
Continuous scan mode............................ 992
Control signal timing ............................ 1600
Control transfer..................................... 1351
Controller area network (RCAN-ET) ... 1017
Controller area network timing............. 1644
CPU .......................................................... 23
Crystal oscillator....................................... 75
CSn assert period expansion................... 317
Cycle steal mode..................................... 422
D
D/A converter (DAC) ........................... 1009
D/A converter characteristics ............... 1652
D/A output hold function in software
standby mode........................................ 1015
Data format in registers ............................ 28
Data formats in memory ........................... 28
Data transfer controller (DTC) ............... 197
Data transfer instructions.......................... 48
Data transfer with interrupt request
signals..................................................... 160
DC characteristics................................. 1592
Dead time compensation ........................ 611
Definition of time quanta...................... 1039
Definitions of A/D conversion accuracy1005
Delayed branch instructions ..................... 31
Direct memory access controller
(DMAC) ................................................. 381
Displacement accessing............................ 33
Divider...................................................... 75
DMA transfer flowchart ......................... 410
DMAC and DTC activation.................... 617
Rev. 1.00 Jun. 26, 2008 Page 1684 of 1692
REJ09B0393-0100
DMAC module timing .......................... 1633
DREQ pin sampling timing .................... 427
DTC activation by interrupt .................... 237
DTC activation sources........................... 210
DTC bus release timing .......................... 233
DTC execution status.............................. 231
DTC vector address ................................ 213
Dual address mode.................................. 419
E
Effective address calculation .................... 34
Electrical characteristics ....................... 1591
Endian ..................................................... 305
EP1 bulk-OUT transfer ......................... 1357
EP2 bulk-IN transfer............................. 1358
EP3 interrupt-IN transfer ...................... 1360
Equation for getting SCBRR value......... 840
Error protection..................................... 1442
Example of USB external circuitry....... 1377
Exception handling ................................... 95
Exception handling state ........................... 62
Exception handling vector table................ 99
Exception source generation immediately
after delayed branch instruction.............. 114
Exceptions triggered by instructions....... 111
External pulse width measurement ......... 610
External request mode............................. 411
External trigger input timing................. 1001
F
Fixed mode ............................................. 415
Flash memory ....................................... 1381
Flash memory configuration ................. 1387
Full-scale error...................................... 1005
G
General illegal instructions ..................... 113