SH7280 Datasheet, PDF (1403/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
USB function
DTC function
Application
Set I[3:0] bits in SR
OUT token reception
Space
in EP1 FIFO?
YES
NO
NACK
Data reception from host
ACK
Set EP1 FIFO full status
(USBIFR0/EP1 FULL = 1)
Interrupt request to CPU*
Clear RRS bit in DTCCR to 0
Set transfer information
(MRA, MRB, SAR, DAR)
Set the start address of transfer
information in DTC vector table
Set DTCE1 bit in DTCERA to 1
Disable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 0)
Read USBEP1 receive data
size register (USBEPSZ1)
[1] Set CRA and CRB to the same value
as the USBEP1 receive data size register
(USBEPSZ1).
Note: * To generate an interrupt request to the CPU,
enable the EP1 FULL interrupt
(USBIER0/EP1 FULL = 1).
Clear RRS bit in DTCCR to 0
Set transfer information
(CRA, CRB)
[1]
Set RRS bit in DTCCR to 1
DTC transfer
request
Clear RXF bit in USDTENDRR
and set bits 7 to 4 in IPR18
(enable interrupts)
Activate DTC
Set EP1DMAE bit in USBDMAR
to 1
Interrupt request
DTC transfer end
to CPU
Clear DTCE1 bit in DTCERA
Receive data transfer end interrupt
Clear EP1DMAE bit in USBDMAR
to 0 and set bits 7 to 4 in IPR18
(disable interrupts)
Enable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 1)
Both
EP1 FIFOs empty?
NO ^{Interrupt request to CPU*}
YES
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
Figure 25.23 Example of DTC Transfer for Bulk-OUT Transfer (EP1)
(When Receive Data Size Cannot be Determined Before Receiving Out Token)
Rev. 1.00 Jun. 26, 2008 Page 1373 of 1692
REJ09B0393-0100