SH7280 Datasheet, PDF (395/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CK
A25 to A0
CSn
WEn
Read
RD/WR
RD
D15 to D0
Write
RD/WR
RD
High
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.38 Wait Timing for SRAM with Byte Selection (BAS = 1)
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
Rev. 1.00 Jun. 26, 2008 Page 365 of 1692
REJ09B0393-0100