SH7280 Datasheet, PDF (1022/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
20.4.2 Continuous Scan Mode
The following example shows the operation when analog input 0, 2, and 3 (AN0, AN2, AN3) are
selected and the A/D conversion is performed in continuous scan mode using the three channels.
This operation also applies to the A/D_1 conversion.
1. Set the ADCS bit in the A/D control register (ADCR) to 0.
2. Set all bits of ANS0, ANS2, and ANS3 in the A/D analog input channel select register
(ADANSR) to 1.
3. Set the OFC and SH bits in the A/D bypass control register_0 (ADBYPSCR_0).
4. Set the ADST bit in the A/D control register (ADCR) to 1 to start A/D conversion.
5. Channels 0 and 2 (GrA) are sampled simultaneously*. As the ANS1 bit in ADANSR is set to
0, channel 1 is not sampled. After this, offset canceling processing (OFC) is performed*. Then
the A/D conversion on channel 0 is started. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR0. In the same way, channel 2 is converted and the
A/D conversion result is transferred to ADDR2. The A/D conversion is not performed on
channel 1.
6. The A/D conversion of channel 3 starts. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR3.
7. When the A/D conversion ends on all the specified channels (AN0, AN2, and AN3), the ADF
bit is set to 1. At this time, if the ADIE bit is set to 1, an ADI interrupt is generated after the
A/D conversion.
8. Steps 5 to 7 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, the A/D conversion stops. After this, if the ADST bit is set to 1, the A/D
conversion starts again and repeats steps 5 to 7.
Note: * The operation depends on the OFC and SH bit settings in ADBYPSCR_0. For details,
see figures 20.6 through 20.9.
Rev. 1.00 Jun. 26, 2008 Page 992 of 1692
REJ09B0393-0100