SH7280 Datasheet, PDF (1365/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.9 USBEP0s Data Register (USBEPDR0s)
USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and
stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only
commands requiring processing on the microcomputer (firmware) side. Commands that this
module automatically processes are not stored. When command data is received normally, the
SETUPTS bit in USB interrupt flag register 0 is set.
As a setup command must be received without fail, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority and the read data is invalid.
Bit: 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W
Undefined R
Description
Register for storing the setup command on control
OUT transfer
Rev. 1.00 Jun. 26, 2008 Page 1335 of 1692
REJ09B0393-0100