SH7280 Datasheet, PDF (751/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
13.6 Usage Notes
13.6.1 Pins States when the Watchdog Timer has Issued a Power-on Reset
A power-on reset issued from the watchdog timer (WDT) initializes the pin-function controller
(PFC) and all I/O port pins thus become general-purpose inputs in accord with the initial PFC
settings. However, when a power-on reset is issued while the port-output enable (POE) setting is
for high-impedance handling by the pins, the pins remain in the output state for an interval of one
cycle of the peripheral clock (Pφ) before switching to operation as general-purpose inputs.
The same condition applies when the WDT issues a power-on reset and short-circuit detection by
the MTU2 has led to high-impedance handling by a pin.
Figure 13.5 shows the situation where timer output has been selected and the WDT issues a
power-on reset while high-impedance handling is in progress due to the POE input.
Pφ
POE input
Pin state
Timer output
PFC setting
Timer output
Timer
output
General-purpose input
High-impedance state
1 period of 1Pφ
General-purpose input
Power-on reset
by the WDT
Figure 13.5 Pin States when the Watchdog Timer Issues a Power-on Reset
Rev. 1.00 Jun. 26, 2008 Page 721 of 1692
REJ09B0393-0100