SH7280 Datasheet, PDF (295/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
Bit Name
20
BAS*
19 to 13  *
12, 11 SW[1:0]
Initial
Value
0
All 0
00
R/W Description
R/W Byte Access Selection when SRAM with Byte
Selection is Used
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
R/W Reserved
Set these bits to 0 when the interface for normal space
or SRAM with byte selection is used.
R/W Number of Delay Cycles from Address, CS0 Assertion
to RD, Wen Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and Wen assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 1.00 Jun. 26, 2008 Page 265 of 1692
REJ09B0393-0100