SH7280 Datasheet, PDF (761/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 14 Compare Match Timer (CMT)
Peripheral clock
(Pφ)
Counter clock
Clock
N+1
CMCNT
N
0
CMCOR
N
CMF
Figure 14.4 Timing of CMF Setting
14.4.3 Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of
the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by
the DMAC.
Rev. 1.00 Jun. 26, 2008 Page 731 of 1692
REJ09B0393-0100