SH7280 Datasheet, PDF (1532/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
28.3.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR5 is initialized to H'EF by a power-on reset but retains its previous value by
a manual reset or in software standby mode. Only byte access is possible.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP
57
56
55

MSTP MSTP MSTP MSTP
53
52
51
50
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP57 1
R/W Module Stop 57
When the MSTP57 bit is set to 1, the supply of the
clock to the SCI0 is halted.
0: SCI0 runs.
1: Clock supply to SCI0 halted.
6
MSTP56 1
R/W Module Stop 56
When the MSTP56 bit is set to 1, the supply of the
clock to the SCI1 is halted.
0: SCI1 runs.
1: Clock supply to SCI1 halted.
Note: Write 1 to this bit in the SH7243.
5
MSTP55 1
R/W Module Stop 55
When the MSTP55 bit is set to 1, the supply of the
clock to the SCI2 is halted.
0: SCI2 runs.
1: Clock supply to SCI2 halted.
4

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 1.00 Jun. 26, 2008 Page 1502 of 1692
REJ09B0393-0100