SH7280 Datasheet, PDF (773/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 15 Watchdog Timer (WDT)
Bit
5
4 to 0
Initial
Bit Name Value R/W Description
RSTS
0
R/W Reset Select
Selects the type of reset when the WTCNT overflows
in watchdog timer mode. In interval timer mode, this
setting is ignored.
0: Power-on reset
1: Manual reset

All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
15.3.4 Notes on Register Access
The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and
watchdog reset control/status register (WRCSR) are more difficult to write to than other registers.
The procedures for reading or writing to these registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a byte or
longword transfer instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,
as shown in figure 15.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the
lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or
WTCSR.
WTCNT write
15
Address: H'FFFE0002
H'5A
87
0
Write data
WTCSR write
15
Address: H'FFFE0000
H'A5
87
0
Write data
Figure 15.2 Writing to WTCNT and WTCSR
Rev. 1.00 Jun. 26, 2008 Page 743 of 1692
REJ09B0393-0100