SH7280 Datasheet, PDF (1405/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

DTC function
Section 25 USB Function Module
Application
Set I[3:0] bits in SR
Clear RRS bit in DTCCR to 0
Set transfer information
(MRA, MRB, SAR, DAR,
[1]
CRA, CRB)
Set RRS bit in DTCCR to 1
Set the start address of transfer
information in DTC vector table
Set DTCE0 bit in DTCERA to 1
Activate DTC
DTC transfer
request
DTC transfer end
Clear DTCE1 bit in DTCERA
Transmit data transfer end interrupt
Interrupt request
to CPU
Clear TXF bit in USDTENDRR
and set bits 3 to 0 in IPR18
(enable interrupts)
Set EP2DMAE bit in USBDMAR
to 1
Clear EP2DMAE bit in USBDMAR
to 0 and set bits 3 to 0 in IPR18
(disable interrupts)
Write 1 to EP2 packet
enable bit
[2]
(USBTRG/EP2 PKTE = 1)
[1] In block transfer mode, the block size set in CRA should be 64 bytes or less.
[2] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Figure 25.25 Example of DTC Transfer for Bulk-IN Transfer (EP2)
(When Transmit Data Size is Determined Before Receiving IN Token)
Rev. 1.00 Jun. 26, 2008 Page 1375 of 1692
REJ09B0393-0100