SH7280 Datasheet, PDF (1373/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.17 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
USBFCLR can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
-
EP3 EP1 EP2
CLR CLR CLR
-
Initial value: 0
0
0
0
0
R/W: -
WWW
-
2
1
0
-
EP0o EP0i
CLR CLR
0
0
0
-
WW
Initial
Bit
Bit Name Value R/W Description
7

0

Reserved
The write value should always be 0.
6
EP3CLR 0
W
EP3 Clear
When 1 is written to this bit, the endpoint 3 transmit
FIFO buffer is initialized.
5
EP1CLR 0
W
EP1 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 1 receive FIFO buffer are initialized.
4
EP2CLR 0
W
EP2 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 2 transmit FIFO buffer are initialized.
3, 2

All 0

Reserved
The write value should always be 0.
1
EP0oCLR 0
W
EP0o Clear
When 1 is written to this bit, the endpoint 0 receive
FIFO buffer is initialized.
0
EP0iCLR 0
W
EP0i Clear
When 1 is written to this bit, the endpoint 0 transmit
FIFO buffer is initialized.
Rev. 1.00 Jun. 26, 2008 Page 1343 of 1692
REJ09B0393-0100