SH7280 Datasheet, PDF (1010/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
20.3.2 A/D Status Registers 0 to 2 (ADSR_0 to ADSR_2)
ADSR is an 8-bit readable/writable register that indicates the status of the A/D converter.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
ADF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Do not overwrite 0 while this flag is 0.
Bit Bit Name
7 to 1 
Initial
Value
All 0
0
ADF
0
R/W
R
R/(W)*
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
A/D End Flag
A status flag that indicates the completion of A/D
conversion.
[Setting condition]
• When A/D conversion on all specified channels is
completed in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC is activated by an ADI interrupt and
ADDR is read
Rev. 1.00 Jun. 26, 2008 Page 980 of 1692
REJ09B0393-0100