SH7280 Datasheet, PDF (1477/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
(2) Interrupts during Programming/Erasing
Do not generate NMI, IRQ, and the other interrupts during programming/erasing of the
downloaded on-chip program.
26.7.3 Other Notes
(1) Download Time of On-Chip Program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock
frequency is 40 MHz, the download for each program takes approximately 10 ms at maximum.
(2) User Branch Processing Intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 26.11 lists the maximum and minimum intervals for initiating
the user branch processing when the CPU clock frequency is 40 MHz.
Table 26.11 Initiation Intervals of User Branch Processing
Processing Name
Programming
Erasing
Maximum Interval
TBD
TBD
Minimum Interval
TBD
TBD
However, when operation is done with CPU clock of 40 MHz, maximum and minimum values of
the time until first user branch processing are as shown in table 26.12.
Table 26.12 Initial User Branch Processing Time
Processing Name
Programming
Erasing
Maximum
TBD
TBD
Minimum
TBD
TBD
(3) Write to Flash-Memory Related Registers by DMAC
While an instruction in on-chip RAM is being executed, the DMAC can write to the SCO bit in
FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure
that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and destroy RAM or a MAT switchover may occur and the CPU get out of control.
Rev. 1.00 Jun. 26, 2008 Page 1447 of 1692
REJ09B0393-0100