SH7280 Datasheet, PDF (1374/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.18 USBDMA Transfer Setting Register (USBDMAR)
USBDMAR enables DMA or DTC transfer between the endpoint 1 and endpoint 2 data registers
and memory by means of the on-chip DMA controller (DMAC) or on-chip data transfer controller
(DTC). Dual address transfer is performed with the transfer size of only on a per-byte basis. In
order to start DMA transfer, DMAC settings must be made in addition to the settings in this
register. For details of DMA transfer, see section 25.8, DMA Transfer. For DTC transfer, DTC
settings must be made in addition to the settings in this register. For details of DTC transfer, see
section 25.9, DTC Transfer.
USBDMAR can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
EP2 EP1
DMAE DMAE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W
Bit
7 to 2
Bit Name

Initial
Value
All 0
1
EP2DMAE*¹ 0
R/W Description
R Reserved
The write value should always be 0.
R/W Endpoint 2 DMA/DTC Transfer Enable
When this bit is set, DMA/DTC transfer is enabled
from memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of space in the FIFO buffer,
a transfer request is asserted for the DMAC or DTC.
In DMA/DTC transfer, when 64 bytes are written to
the FIFO buffer, the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred. If there is still space in the other of the
two FIFOs, a transfer request is asserted for the
DMAC or DTC again. However, if the size of the data
packet to be transmitted is less than 64 bytes, the
EP2 packet enable bit is not set automatically, and so
should be set by the CPU with a DMA/DTC transfer
end interrupt.
Also, as EP2-related interrupt requests to the CPU
are not automatically masked, interrupt requests
should be masked as necessary in the interrupt
enable register.
Rev. 1.00 Jun. 26, 2008 Page 1344 of 1692
REJ09B0393-0100