SH7280 Datasheet, PDF (1458/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
When the SCO bit is set to 1, download is started automatically. When execution returns to the
user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of the DPFR parameter. Before
the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter,
that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value
other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcontroller processing, so VBR
need to be set to H'80000000. Thirty-two NOP instructions are executed immediately after the
instructions that set the SCO bit to 1.
1. The user MAT space is switched to the on-chip program storage area.
2. After the selection condition of the download program and the address set in FTDAR are
checked, the transfer processing is executed starting to the on-chip RAM address specified
by FTDAR.
3. The SCO bits in FCCS, FPCS, and FECS are cleared to 0.
4. The return value is set to the DPFR parameter.
5. After the on-chip program storage area is returned to the user MAT space, execution
returns to the user procedure program.
After download is completed and the user procedure program is running, the VBR setting can
be changed.
The notes on download are as follows.
In the download processing, the values of the general registers of the CPU are retained.
During the download processing, interrupts must not be generated. For details on the
relationship between download and interrupts, see section 26.7.2, Interrupts during
Programming/Erasing.
Since a stack area of maximum 256 bytes is used, an area of at least 128 bytes must be saved
before setting the SCO bit to 1.
If flash memory is accessed by the DMAC during downloading, operation cannot be
guaranteed. Therefore, access by the DMAC must not be executed.
(2.4) FKEY is cleared to H'00 for protection.
Rev. 1.00 Jun. 26, 2008 Page 1428 of 1692
REJ09B0393-0100