SH7280 Datasheet, PDF (1463/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 26.8.2, Areas for Storage of the Procedural Program
and Data for Programming.
For the downloaded on-chip program area, see the RAM map for programming/erasing in figure
26.11.
A single divided block is erased by one erasing processing. For block divisions, see figure 26.4.
To erase two or more blocks, update the erase block number and perform the erasing processing
for each block.
(3.1) Select the on-chip program to be downloaded and the download destination address
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see the description in section 26.5.3
(2), Programming Procedure in User Program Mode.
(3.2) Set the FEBS parameter necessary for erasure
Set the erase block number of the user MAT in the flash erase block select parameter (FEBS:
general register R4). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
Rev. 1.00 Jun. 26, 2008 Page 1433 of 1692
REJ09B0393-0100