SH7280 Datasheet, PDF (1413/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

26.2 Overview
26.2.1 Block Diagram
ROM cache address bus
ROM cache data bus (128 bits)
Section 26 Flash Memory
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
Control unit
Memory MAT unit
User MAT: 256 Kbytes,
512 Kbytes,
768 Kbytes,
1 Mbyte
User boot MAT: 12 Kbytes*
Flash memory
FWE pin
Mode pins
Operating
mode
[Legend]
FCCS: Flash code control and status register
FPCS: Flash program code select register
FECS: Flash erase code select register
FKEY: Flash key code register
FMATS: Flash MAT select register
FTDAR: Flash transfer destination address register
Note: * Not available in the SH7243
Figure 26.1 Block Diagram of Flash Memory
Rev. 1.00 Jun. 26, 2008 Page 1383 of 1692
REJ09B0393-0100