SH7280 Datasheet, PDF (207/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 7 User Break Controller (UBC)
7.3.7 Break Address Register_2 (BAR_2)
BAR_2 is a 32-bit readable/writable register. BAR_2 specifies the address used as a break
condition in channel 2. The control bits CD2_1 and CD2_0 in the break bus cycle register_2
(BBR_2) select one of the three address buses for a break condition of channel 2. BAR_2 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA2_31 BA2_30 BA2_29 BA2_28 BA2_27 BA2_26 BA2_25 BA2_24 BA2_23 BA2_22 BA2_21 BA2_20 BA2_19 BA2_18 BA2_17 BA2_16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BA2_15BA2_14BA2_13BA2_12BA2_11BA2_10 BA2_9 BA2_8 BA2_7 BA2_6 BA2_5 BA2_4 BA2_3 BA2_2 BA2_1 BA2_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BA2_31 to All 0
BA2_0
R/W Break Address 2
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 2.
When the C bus and instruction fetch cycle are
selected by BBR_2, specify an FAB address in bits
BA2_31 to BA2_0.
When the C bus and data access cycle are selected by
BBR_2, specify an MAB address in bits BA2_31 to
BA0_2.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_2 to 0.
Rev. 1.00 Jun. 26, 2008 Page 177 of 1692
REJ09B0393-0100