SH7280 Datasheet, PDF (657/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNTS P − 1
P
H'0000
Buffer transfer
signal
Temporary
register
N
Compare
register
n
N
Figure 11.108 Transfer Timing from Temporary Register to Compare Register
11.6.2 Interrupt Signal Timing
(1) TGF Flag Setting Timing in Case of Compare Match
Figures 11.109 and 110 show the timing for setting of the TGF flag in TSR on compare match,
and TGI interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 11.109 TGI Interrupt Timing (Compare Match)
Rev. 1.00 Jun. 26, 2008 Page 627 of 1692
REJ09B0393-0100