SH7280 Datasheet, PDF (924/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.3.6 SS Control Register 2 (SSCR2)
SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit: 7
6
5
4
3
2
1
0
SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS -
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R R
Initial
Bit
Bit Name Value R/W
Description
7
SDOS
0
R/W
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
TTL or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, see section 18.4.3, Relationship between Data
Input/Output Pins and Shift Register.
0: TTL output
1: NMOS open drain output
6
SSCKOS 0
R/W
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a TTL or an
NMOS open drain output.
0: TTL output
1: NMOS open drain output
5
SCSOS 0
R/W
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a TTL or an
NMOS open drain output.
0: TTL output
1: NMOS open drain output
4
TENDSTS 0
R/W
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
Rev. 1.00 Jun. 26, 2008 Page 894 of 1692
REJ09B0393-0100