SH7280 Datasheet, PDF (1643/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

CK
A25 to A0
CSn
RD/WR
RD
D31 to D0
Section 31 Electrical Characteristics
T1
Tw
Twx
T2B
Twb
T2B
t_AD1
t_AD2
tAD2
t_AD1
t_CSD1 t_AS
t_CSD1
tRWD1
t_RSD
tRDS3
t_RDH3
t_RWD1
t_RSD
t_RDS3
t_RDH3
WEn
BS
DACKn
TENDn*
WAIT
t_BSD
t_BSD
t_DACD
t_WTH
t_WTH
t_WTS
t_WTS
tDACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.18 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two-Cycle Burst)
Rev. 1.00 Jun. 26, 2008 Page 1613 of 1692
REJ09B0393-0100