SH7280 Datasheet, PDF (34/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Items
Data transfer
controller (DTC)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Power-down modes
Specification
• Data transfer activated by an on-chip peripheral module interrupt can
be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is
specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes
Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU.
A CPU interrupt can be requested after one data transfer completion.
• A CPU interrupt can be requested after all specified data transfer
completion.
• Clock mode: Input clock can be selected from external input (EXTAL)
or crystal resonator
• Input clock can be multiplied by 8 (max.) by the internal PLL circuit
• Five types of clocks generated:
 CPU clock: Maximum 100 MHz
 Bus clock: Maximum 50 MHz
 Peripheral clock: Maximum 50 MHz
 Timer clock: Maximum 100 MHz
 AD clock: Maximum 50 MHz
• On-chip one-channel watchdog timer
• A counter overflow can reset the LSI
• Three power-down modes provided to reduce the current consumption
in this LSI
 Sleep mode
 Software standby mode
 Module standby mode
Rev. 1.00 Jun. 26, 2008 Page 4 of 1692
REJ09B0393-0100