SH7280 Datasheet, PDF (939/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 18.7 shows an example of reception operation, and figure 18.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
In continuous reception as the slave device in SSU mode, be sure to read SSRDR before reception
of the next frame starts. If reception of a next frame starts before clearing RDRF to 0, then read
SSRDR before completing the reception of the next frame, CE in SSSR will be set to 1 at the end
of the next frame.
If reception of the next frame starts before RDRF is cleared to 0 then SSRDR will not be read until
the end of completion, neither CE nor ORER in SSSR will be set but the received data will be
discarded.
Rev. 1.00 Jun. 26, 2008 Page 909 of 1692
REJ09B0393-0100