SH7280 Datasheet, PDF (191/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
Figures 6.13 and 6.14 show block diagrams of interrupt control.
IRQ edge detector
(in standby)
Standby
cancellation
identifier
Standby control
IRQ pin
IRQ detection
Interrupt controller
Interrupt priority
identifier
CPU interrupt request
DTCER
DTCE clearing
DTC
DTC activation
request
DTCECLR
Transfer end
IRQ flag clearing by DTC
Figure 6.13 Interrupt Control Block Diagram
Interrupt source
Interrupt controller
Interrupt priority
identifier
CPU interrupt request
Decoding
DMAC
Bits RS[3:0]
in CHCR
DTC
DMAC activation
request
Interrupt source
flag clearing
DTCER
DTCE clearing
Interrupt source flag clearing by DTC
DTC activation
request
DTCECLR
Transfer end
Interrupt source
flag clearing
by DMAC
Figure 6.14 Block Diagram of Controlling an On-Chip Peripheral Module Interrupt
Rev. 1.00 Jun. 26, 2008 Page 161 of 1692
REJ09B0393-0100