SH7280 Datasheet, PDF (1388/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.5.5 EP2 Bulk-IN Transfer (Dual FIFOs)
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes
without being aware of this dual-FIFO configuration. However, one data write is performed for
one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at
one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64-
byte write.
When performing bulk-IN transfer, as there is no valid data in the FIFOs on reception of the first
IN token, a USBIFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the
USBIER0/EP2EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs
are empty, and so an EP2 FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2EMPTY is cleared to 0. If at least one
FIFO is empty, USBIFR0/EP2EMPTY is set to 1. When ACK is returned from the host after data
transmission is completed, the FIFO used in the data transmission becomes empty. If the other
FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to USBIER0/EP2EMPTY and disable
interrupt requests.
Rev. 1.00 Jun. 26, 2008 Page 1358 of 1692
REJ09B0393-0100