SH7280 Datasheet, PDF (993/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3)
19.5 Interrupt Requests
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost/overrun error. Table 19.4 shows the
contents of each interrupt request.
Table 19.4 Interrupt Requests
Interrupt Request
Transmit data Empty
Transmit end
Receive data full
STOP recognition
NACK detection
Arbitration lost/
overrun error
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TDRE = 1) ^• (TIE = 1)
(TEND = 1) ^• (TEIE = 1)
(RDRF = 1) ^• (RIE = 1)
(STOP = 1) ^• (STIE = 1)
{(NACKF = 1) + (AL = 1)} ^•
(NAKIE = 1)
I²C Bus
Format
√
√
√
√
√
√
Clocked Synchronous
Serial Format
√
√
√


√
When the interrupt condition described in table 19.4 is 1, the CPU executes an interrupt exception
handling. Note that a TXI or RXI interrupt can activate the DMAC or DTC if the setting for
DMAC or DTC activation has been made. In such a case, an interrupt request is not sent to the
CPU. Interrupt sources should be cleared in the exception handling. The TDRE and TEND bits are
automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically
cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit
data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of
one byte may be transmitted.
Rev. 1.00 Jun. 26, 2008 Page 963 of 1692
REJ09B0393-0100