SH7280 Datasheet, PDF (1423/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
Table 26.4 (2) Parameter Configuration
Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Download pass/fail result DPFR
R/W Undefined On-chip RAM* 8, 16, 32
Flash pass/fail result
FPFR
R/W Undefined R0 of CPU 8, 16, 32
Flash multipurpose address FMPAR
area
R/W Undefined R5 of CPU 8, 16, 32
Flash multipurpose data
destination area
FMPDR
R/W Undefined R4 of CPU 8, 16, 32
Flash erase block select
FEBS
R/W Undefined R4 of CPU 8, 16, 32
Flash program and erase
frequency control
FPEFEQ
R/W Undefined R4 of CPU 8, 16, 32
Flash user branch address FUBRA
set parameter
R/W Undefined R5 of CPU 8, 16, 32
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Table 26.5 Register/Parameter and Target Mode
Initiali- Program-
RAM
Download zation ming
Erasure Read Emulation
Programming/ FCCS
√
erasing interface _FPCS
√
registers
PECS
√
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FKEY
√
FMATS —
—
√
—
√*¹
√
—
—
√*¹
√*²
—
FTDAR √
—
—
—
—
—
Programming/ DPFR
√
erasing interface _FPFR
—
parameters
FPEFEQ —
—
—
√
√
√
—
—
—
—
√
—
—
—
—
—
FUBRA —
√
—
—
—
—
FMPAR —
—
√
—
—
—
FMPDR —
—
√
—
—
—
FEBS
—
—
—
√
—
—
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
Rev. 1.00 Jun. 26, 2008 Page 1393 of 1692
REJ09B0393-0100