SH7280 Datasheet, PDF (288/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
3

0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
HIZCKIO 0
R/W High-Z CK Control
Specifies the state in CK standby mode and when bus
mastership is released.
0: CK is in high impedance state in standby mode and
bus-released state.
1: CK is driven in standby mode and bus-released
state.
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0,
BS, CSn, RD/WR, WEn/DQMxx, AH, and RD. At bus-
released state, these pins are in high-impedance state
regardless of the setting value of the HIZMEM bit.
0: High impedance in standby mode.
1: Driven in standby mode
0
HIZCNT
0
R/W High-Z Control
Specifies the state in standby mode and bus-released
state for CKE, RASL, CASL, RASU, and CASU.
0: CKE, RASL, CASL, RASU, and CASU are in high-
impedance state in standby mode and bus-released
state.
1: CKE, RASL, CASL, RASU, and CASU are driven in
standby mode and bus-released state.
Rev. 1.00 Jun. 26, 2008 Page 258 of 1692
REJ09B0393-0100