SH7280 Datasheet, PDF (105/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1) PLL Circuit
The PLL circuit multiplies the input clock frequency from the crystal oscillator or EXTAL pin by
8.
(2) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the
XTAL pin or EXTAL pin. This can be used according to the clock operating mode.
(3) Divider
The divider generates a clock signal at the operating frequency used by the internal clock (Iφ), bus
clock (Bφ), peripheral clock (Pφ), MTU2S clock (Mφ), or AD clock (Aφ). The operating
frequency can be 1, 1/2, 1/4, or 1/8 times the output frequency of the PLL circuit. The division
ratio is set in the frequency control register (FRQCR). USB clock (Uφ) is set as fixed 1/2 and
when generating USB clock with a divider, set the crystal resonator to 12 MHz.
(4) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the frequency control
register (FRQCR).
(5) Standby Control Circuit
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or sleep or software standby mode.
(6) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CK pin during software standby mode, and the frequency
division ratios of the internal clock (Iφ), bus clock (Bφ), and peripheral clock (Pφ).
(7) MTU2S Clock Frequency Control Register (MCLKCR)
The MTU2S clock frequency control register (MCLKCR) has control bits assigned for the
following functions: MTU2S clock (Mφ) output/non-output and the frequency division ratio.
Rev. 1.00 Jun. 26, 2008 Page 75 of 1692
REJ09B0393-0100