SH7280 Datasheet, PDF (39/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

1.2 Block Diagram
Section 1 Overview
SH-2A
CPU core
On-chip ROM
On-chip RAM
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
CPU bus
(C bus)
(I clock)
User break
controller (UBC)
Internal bus (B clock)
Bus state
controller
(BSC)
Peripheral
bus controller
Data transfer
controller
(DTC)
Direct memory
access controller
(DMAC)
Peripheral bus (P clock)
Pin function
controller
(PFC)
I/O
ports
Multi-function
timer pulse
unit 2S
(MTU2S)
Multi-function
timer pulse
unit 2
(MTU2)
Watchdog
timer
(WDT)
12-bit A/D
converter
(ADC)
Port output
enable 2
(POE2)
Compare
match
timer
(CMT)
Serial
communication
interface
(SCI)
Serial
communication
interface
with FIFO
(SCIF)
D/A
converter
(DAC) *²
Controller
area network
(RCAN-ET) *²
I2C bus
interface 3
(IIC3) *¹
Universal
serial bus
(USB) *¹
User debugging
interface
(H-UDI)
Interrupt
controller
(INTC)
Clock pulse
generator
(CPG)
Power-down
mode
control
Synchronous
serial
communication
interface
(SSU) *¹
Notes: 1. Only in SH7286 and SH7285
2. Only in SH7286
Figure 1.1 Block Diagram
Rev. 1.00 Jun. 26, 2008 Page 9 of 1692
REJ09B0393-0100