SH7280 Datasheet, PDF (178/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
6.6.2 Stack after Interrupt Exception Handling
Figure 6.3 shows the stack after interrupt exception handling.
Address
4n – 8 PC*¹
4n – 4 SR
4n
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executed instruction
2. Always make sure that SP is a multiple of 4.
Figure 6.3 Stack after Interrupt Exception Handling
Rev. 1.00 Jun. 26, 2008 Page 148 of 1692
REJ09B0393-0100