SH7280 Datasheet, PDF (382/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
(11) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing
the CKE signal to the low level in the non-access cycle. This power-down mode can effectively
lower the power consumption in the non-access cycle. However, please note that if an access
occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the
CKE in order to cancel power-down mode.
Figure 9.31 shows the access timing in power-down mode.
Power-down Tnop Tr
CK
Tc1
Td1
Tde
Tap Power-down
CKE
A25 to A0
A12/A11*¹
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.31 Power-Down Mode Access Timing
Rev. 1.00 Jun. 26, 2008 Page 352 of 1692
REJ09B0393-0100