SH7280 Datasheet, PDF (231/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
Initial
Bit Bit Name Value
R/W
1, 0 
Undefined 
[Legend]
x: Don't care
Description
Reserved
The write value should always be 0.
8.2.2 DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit: 7
6
5
4
3
2
1
0
CHNE CHNS DISEL DTS
DM[1:0]
-
-
Initial value: *
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
* : Undefined
Initial
Bit Bit Name Value
R/W
7
CHNE
Undefined 
6
CHNS
Undefined 
5
DISEL
Undefined 
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
8.5.6, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
DTC Interrupt Select
When this bit is set to 1, an interrupt request is generated
to the CPU every time a data transfer or a block data
transfer ends. When this bit is set to 0, a CPU interrupt
request is only generated when the specified number of
data transfers ends.
Rev. 1.00 Jun. 26, 2008 Page 201 of 1692
REJ09B0393-0100