SH7280 Datasheet, PDF (371/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*¹
CS3
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tnop Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.23 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank,
CAS Latency 1)
Rev. 1.00 Jun. 26, 2008 Page 341 of 1692
REJ09B0393-0100