SH7280 Datasheet, PDF (411/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
Section 10 Direct Memory Access Controller (DMAC)
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1 Features
• Number of channels selectable: Eight channels (channels 0 to 7) max.
CH0 to CH2 channels (SH7285, SH7243) and CH0 to CH3 channels (SH7286) can only
receive external requests.
• 4-Gbyte physical address space
• Transfer data length is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
 External request
 On-chip peripheral module request
 Auto request
The following modules can issue on-chip peripheral module requests.
 Two SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, two
CMT sources, two USB sources, two SSU sources, and one RCAN source
• Selectable bus modes
 Cycle steal mode (normal mode and intermittent mode)
 Burst mode
• Selectable channel priority levels: The channel priority levels are selectable between fixed
mode and round-robin mode.
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-
data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
• External request detection: There are following four types of DREQ input detection.
 Low level detection
 High level detection
 Rising edge detection
 Falling edge detection
Rev. 1.00 Jun. 26, 2008 Page 381 of 1692
REJ09B0393-0100