English
Language : 

SH7280 Datasheet, PDF (1648/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
Section 31 Electrical Characteristics
Tr
Tc1
Trwl
CK
A25 to A0
A12/A11*1
tAD1
tAD1
tAD1
Row
address
Column
address
tAD1
tAD1
tAD1
WRITA
command
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
tCSD1
tCSD1
tRWD1
tRWD1
tRWD1
tRASD1
tRASD1
tCASD1
tCASD1
tDQMD1
tDQMD1
tWDD2
tWDH2
tBSD
tBSD
CKE
DACKn
TENDn*2
tDACD
(High)
tDACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.23 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 1 Cycle)
Rev. 1.00 Jun. 26, 2008 Page 1618 of 1692
REJ09B0393-0100