SH7280 Datasheet, PDF (273/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
8.9.6 Access to DTC Registers through DTC
Do not access the DMAC or DTC registers by using DTC operation. Do not access the DTC
registers by using DMAC operation.
8.9.7 Notes on IRQ Interrupt as DTC Activation Source
• When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request
an interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be held low
until the CPU accepts the interrupt.
8.9.8 Note on SCI or SCIF as DTC Activation Sources
When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag in
the SCI must not be used as the transfer end flag.
When the TXIF interrupt from the SCIF is specified as a DTC activation source, the TEND flag in
the SCIF must not be used as the transfer end flag.
8.9.9 Clearing Interrupt Source Flag
The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt
handler in the same way as for general interrupt source flags. For details, refer to section 6.10,
Usage Note.
8.9.10 Conflict between NMI Interrupt and DTC Activation
When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the
NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated.
It takes 3Bφ + 2Pφ for checking DTC stop by the NMI, 3Bφ + 2Pφ for checking DTC activation
by the IRQ, and 1Bφ + 1Pφ to 4Bφ + 1Pφ for checking DTC activation by the peripheral module.
8.9.11 Note on USB as DTC Activation Sources
To generate a CPV interrupt when a DTC transfer activated by the USB is completed, refer to the
procedure described in section 25, USB Function Module.
Rev. 1.00 Jun. 26, 2008 Page 243 of 1692
REJ09B0393-0100