SH7280 Datasheet, PDF (1367/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.11 USBEP2 Data Register (USBEPDR2)
USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When transmit data is written
to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit
data is fixed, and the dual buffer is switched over. Transmit data for this FIFO buffer can be
transferred by DMA or DTC (dual address transfer byte by byte).
USBEPDR2 can be initialized by means of the EP2CLR bit in USBFCLR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name Value
R/W Description
31 to 0* D31 to D0 Undefined W
Data register for endpoint 2 transfer
Note: * 7 to 0 bits for DMA or DTC transfer.
Rev. 1.00 Jun. 26, 2008 Page 1337 of 1692
REJ09B0393-0100