SH7280 Datasheet, PDF(1050/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (1050/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)

Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole

RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord

(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,

LongWord access means the two consecutive accesses.

â¢ Micro Processor Interface (MPI)

The MPI allows communication between the Renesas CPU and RCAN-ETâs

registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic

that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so

that the RCAN-ET can automatically exit the Sleep mode.

It contains registers such as MCR, IRR, GSR and IMR.

â¢ Mailbox

The Mailboxes consists of RAM configured as message buffers and registers. There are 16

Mailboxes, and each mailbox has the following information.

<RAM>

ï£§ CAN message control (identifier, rtr, ide,etc)

ï£§ CAN message data (for CAN Data frames)

ï£§ Local Acceptance Filter Mask for reception

<Registers>

ï£§ CAN message control (dlc)

ï£§ 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-

Transmission for Remote Request bit, New Message Control bit

â¢ Mailbox Control

The Mailbox Control handles the following functions:

ï£§ For received messages, compare the IDs and generate appropriate RAM addresses/data to

store messages from the CAN Interface into the Mailbox and set/clear appropriate registers

accordingly.

ï£§ To transmit messages, RCAN-ET will run the internal arbitration to pick the correct

priority message, and load the message from the Mailbox into the Tx-buffer of the CAN

Interface and set/clear appropriate registers accordingly.

ï£§ Arbitrates Mailbox accesses between the CPU and the Mailbox Control.

ï£§ Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and

MBIMR.

Rev. 1.00 Jun. 26, 2008 Page 1020 of 1692

REJ09B0393-0100

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