SH7280 Datasheet, PDF (407/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
9.5.12 Others
(1) Reset
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state
after the internal reset is synchronized with the internal clock. All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At manual reset, only the current bus cycle being executed is completed. Since the RTCNT
continues counting up during manual reset signal assertion, a refresh request occurs to initiate the
refresh cycle.
(2) Access from the Side of the LSI Internal Bus Master
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the internal bus before the previous external bus cycle is completed in a write cycle. If
the on-chip module is read or written after the external low-speed memory is written, the on-chip
module can be accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than
the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read
cycle is initiated before the previous write cycle is completed. Note, however, that if both the
DMA source and destination addresses exist in external memory space, the next write cycle will
not be initiated until the previous write cycle is completed.
Changing the registers in the BSC while the write buffer is operating may disrupt correct write
access. Therefore, do not change the registers in the BSC immediately after a write access. If this
change becomes necessary, do it after executing a dummy read of the write data.
Rev. 1.00 Jun. 26, 2008 Page 377 of 1692
REJ09B0393-0100