SH7280 Datasheet, PDF (332/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
11
DTBST
0
R/W DTC Burst Enable
Selects whether the DTC continues operation without
releasing the bus when multiple DTC activation
requests are generated.
0: The DTC releases the bus every time a DTC
activation request has been processed.
1: The DTC continues operation without releasing the
bus until all DTC activation requests have been
processed.
Notes: When this bit is set to 1, the following restrictions
apply.
1. Clock setting through the frequency control
register (FRQCR) must be Iφ : Bφ : Pφ: Mφ:
Aφ = 8 : 4 : 4 : 4 : 4, 4 : 2 : 2 : 2 : 2, or 2 : 1 : 1
: 1 : 1.
2. The vector information must be stored in the
on-chip ROM or on-chip RAM.
3. The transfer information must be stored in
the on-chip RAM.
4. Transfer must be between the on-chip RAM
and an on-chip peripheral module or
between the external memory and an on-
chip peripheral module.
5. Do not set the DTBST bit to 1, when the
activation source is low-level setting for
IRQ7 to IRQ0 and the RRS bit is set to 1.
Rev. 1.00 Jun. 26, 2008 Page 302 of 1692
REJ09B0393-0100